Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device, which is capable of substantially preventing a high aspect ratio pattern from leaning.
A high aspect ratio pattern is required in a process for fabricating a semiconductor device such as DRAM or a NAND flash device. The high aspect ratio pattern may include a trench for element isolation, a gate, a storage node and so on. In a vertical cell with 4F2 structure, a high aspect ratio trench may be provided to form a buried bit line.
In such a high aspect ratio pattern, a ratio of depth D to line width L is defined as an aspect ratio (D/L).
During an etching process for forming a pattern, etching residues are formed on the sidewalls of the pattern and the bottom. The etching residues are removed by a subsequent cleaning process. The etching residues are referred to as post etch residues (PER).
However, due to the increase of the aspect ratio, pattern leaning frequently occurs after the cleaning process, even though pattern leaning may not occur before the cleaning process.
FIG. 1 is a photograph showing a case in which pattern leaning occurs after the subsequent cleaning process. Referring to FIG. 1, it can be seen that a bridge occurs between adjacent patterns due to the pattern leaning.
Furthermore, as semiconductor devices shrink, the aspect ratio rapidly increases. Therefore, when the design rule is equal to or less than 20 nm, it is difficult to prevent pattern leaning during a cleaning process for a pattern having an aspect ratio of 15 or more.